I-Lun Tseng   I-Lun Tseng    I-Lun Tseng



E-mail: iltseng@acm.org
Personal Website: http://www.itseng.org
     
    
     
     

I-Lun Tseng received a B.S. degree in Computer Science and Engineering from Yuan Ze University, an M.S. degree in Computer Science from National Tsing Hua University, and a Ph.D. degree in Electrical Engineering from the University of Queensland. He worked as an R&D software engineer at Avant! Corporation (merged with Synopsys, Inc.) in Taipei between 1999 and 2002. He was an Assistant Professor in the Department of Computer Science and Engineering at Yuan Ze University between 2008 and 2013. He joined TSMC in 2013 and is currently a Principal Engineer. His research interests include algorithms for VLSI physical design automation, mathematical programming, constraint programming, computational geometry, parallel programming, and analog design methodologies.
   

Education
Publications
Book
   [B01]  

I-Lun Tseng, Estimation of Analog Layout Parasitics with Parameterized Polygons: Algorithms for Partitioning Parameterized Polygons, LAP Lambert Academic Publishing, December 8, 2009.  [Link]  [ISBN-10: 3838330307]  [ISBN-13: 978-3838330303]  [NSC-98-2221-E-155-053]
   

Journal Papers / Book Chapters
  [J03]   Yao-Lin Chang and I-Lun Tseng, “A Parallel Dual-Scanline Algorithm for Partitioning Parameterized 45-Degree Polygons,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 18, No. 4, Article No. 59, October 2013.  (SCI-E, EI, DBLP)  [NSC-101-2221-E-155-074]  [pdf]
   
  [J02]   I-Lun Tseng, Huan-Wen Chen, Yung-Wei Kao, and Che-I Lee, “Obstacle-Aware Longest-Path Routing with Constraint Programming and Parallel MILP,” IAENG Transactions on Engineering Technologies Volume 6, America Institute of Physics, pp. 18-28, October 2011.  [Link]  [ISBN: 978-0-7354-0933-0]  (EI)  [NSC-98-2221-E-155-053]  [NSC-99-2221-E-155-088]
   
     [J01]    I-Lun Tseng and Adam Postula, “Partitioning Parameterized 45-Degree Polygons with Constraint Programming,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 13, No. 3, Article No. 52, July 2008.  (SCI-E, EI, DBLP)  [pdf]
   
Conference Papers
  [C16]   Yao-I Tseng, I-Lun Tseng, and Adam Postula, Boolean Mask Operations on Parameterized 45-Degree Polygons, In Proceedings of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 453-456, Columbus, Ohio, USA, August 4-7, 2013.  [NSC-101-2221-E-155-074]  [pdf]
    
  [C15]   Yao-I Tseng, I-Lun Tseng, Tsao Hsiao Huang, and Adam Postula, Fast Partitioning of Parameterized 45-Degree Polygons into Parameterized Trapezoids,” In Proceedings of IEEE International New Circuits and Systems Conference (NEWCAS), Paris, France, June 16-19, 2013.  (Regular Paper)  [NSC-101-2221-E-155-074]  [pdf]
    
  [C14]   Zhi-Wen Wang, I-Lun Tseng, and Adam Postula, Procedural Module Generation for Parameterized Layouts,” In Proceedings of IEEE TENCON Spring Conference (TENCON-SPRING), pp. 548-551, Sydney, New South Wales, Australia, April 17-19, 2013.  (Regular Paper)  [NSC-101-2221-E-155-074]  [pdf]
   
  [C13]   Hsin-Hung Liu, Rung-Bin Lin, and I-Lun Tseng, Relocatable and Resizable SRAM Synthesis for Via Configurable Structured ASIC,” In Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), pp. 494-501, Santa Clara, California, USA, March 4-6, 2013.  [pdf]
   
  [C12]  

Zhi-Wen Wang, I-Lun Tseng, and Adam Postula, Design and Representation of Parameterized Layouts for Octagonal Spiral Inductors,” In Proceedings of IEEE International Symposium on Next-Generation Electronics (ISNE), pp. 333-336, Kaohsiung, Taiwan, February 25-26, 2013.  [1st Place in Students' Best Paper Competition - Poster Session Group A]  [NSC-101-2221-E-155-074]  [pdf]
    

  [C11]  

Cheng-Yuan Chang and I-Lun Tseng, A Parallel Algorithm for Constructing Obstacle-Avoiding Rectilinear Steiner Minimal Trees on Multi-Core Systems, In Proceedings of International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA), Vol. 2, pp. 613-618, Las Vegas, Nevada, USA, July 16-19, 2012.  (Regular Research Paper)  (acceptance rate: 28%)  [NSC-99-2221-E-155-088]  [pdf]
   

     [C10]   

I-Lun Tseng, Yung-Wei Kao, Cheng-Yuan Chang, and Adam Postula, Dogleg Channel Routing with Parallel Mixed Integer Linear Programming Solvers, In Proceedings of International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA), Vol. 2, pp. 533-539, Las Vegas, Nevada, USA, July 18-21, 2011.  (Regular Research Paper)  (acceptance rate: 23%)  [NSC-99-2221-E-155-088]  [pdf]
  

     [C09]   

I-Lun Tseng, Che-I Lee, and Huan-Wen Chen, Efficient Partitioning of Parameterized 45-Degree Polygons with Mixed ILP, In Proceedings of IEEE Region 10 Conference (TENCON), pp. 1531-1534, Fukuoka, Japan, November 21-24, 2010.  (Regular Paper)  (acceptance rate for regular paper: 42.7%)  (EI)  [NSC-98-2221-E-155-053]  [NSC-99-2221-E-155-088]  [pdf]
 

     [C08]   

Che-I Lee, Huan-Wen Chen, and I-Lun Tseng, Obstacle-Avoiding Switchbox Routing with CP and Parallel MILP, In Proceedings of Annual International Conference on Advances in Distributed and Parallel Computing (ADPC), pp. 45-50, Singapore, November 1-2, 2010.  [NSC-98-2221-E-155-053]  [NSC-99-2221-E-155-088]  [pdf]
  

     [C07]   

I-Lun Tseng, Huan-Wen Chen, and Che-I Lee, Obstacle-Aware Longest-Path Routing with Parallel MILP Solvers, In Proceedings of the World Congress on Engineering and Computer Science - International Conference on Circuits and Systems (WCECS-ICCS), Vol. 2, pp. 827-831, San Francisco, CA, USA, October 20-22, 2010.  (acceptance rate: 54.94%)  [Best Paper Award Nomination]  [NSC-98-2221-E-155-053]  [NSC-99-2221-E-155-088]  [pdf]
 

     [C06]   

I-Lun Tseng, Huan-Wen Chen, Che-I Lee, and Adam Postula, Constraint-Based Dogleg Channel Routing with Via Minimization, In Proceedings of the 12th International Conference on Artificial Intelligence (ICAI), Vol. 2, pp. 666-672, Las Vegas, Nevada, USA, July 12-15, 2010.  (Regular Research Paper)  (acceptance rate: 28%)  (EI, DBLP)  [NSC-98-2221-E-155-053]  [pdf]
  

     [C05]   

I-Lun Tseng, Che-I Lee, Huan-Wen Chen, and Adam Postula, Decomposition of Parameterized Orthogonal Polygons via Formal Transformations, In Proceedings of the International Conference on Digital Content (ICDC), pp. 871-877, Chung-Li, Taiwan, December 2009.  [NSC-98-2221-E-155-053]
  

     [C04]   

I-Lun Tseng and Adam Postula, An Efficient Algorithm for Partitioning Parameterized Polygons into Rectangles, In Proceedings of the 16th ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 366-371, Philadelphia, Pennsylvania, USA, April 30 - May 2, 2006.  (acceptance rate: 37%)  (EI, DBLP)  [pdf]
  

     [C03]   

I-Lun Tseng, Adam Postula, and Lech Jóźwiak, “Symbolic Extraction for Estimating Analog Layout Parasitics in Layout-Aware Synthesis,” In Proceedings of the 12th IEEE International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES), Vol. 1, pp. 195-199, Kraków, Poland, June 22-25, 2005.  [pdf]
  

     [C02]   

I-Lun Tseng and Adam Postula, “A Layout-Aware Circuit Sizing Model Using Parametric Analysis,” In Proceedings of the Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 235-240, Kanazawa, Japan, October 18-19, 2004.  [pdf]
  

     [C01]   

I-Lun Tseng and Adam Postula, “GBLD: A Formal Model for Layout Description and Generation,” In Proceedings of the Forum on Specification & Design Languages (FDL), Vol. 2, pp. 660-670, Lille, France, September 13-17, 2004.  (DBLP)  [pdf]
  

Report
  • I-Lun Tseng, Automation of Layout-Aware Analog Integrated Circuit Design, Ph.D. Confirmation Report, School of Information Technology and Electrical Engineering, The University of Queensland, Australia, Jan. 27, 2005.

Theses
  • I-Lun Tseng, “Estimation of Analog Layout Parasitics with Parameterized Polygons,” Ph.D. Thesis, School of Information Technology and Electrical Engineering, The University of Queensland, Australia, February 2008. [pdf] 

  • I-Lun Tseng, On the Design of Interoperability Test Sequence for Communication Protocols, Master Thesis, Department of Computer Science, National Tsing Hua University, Taiwan, May 1999.

Professional Experience
  • September 2013 - Present, Principal Engineer,
    Taiwan Semiconductor Manufacturing Company (TSMC), Hsin-Chu, Taiwan
       
  • August 2008 - July 2013, Assistant Professor,
    Department of Computer Science & Engineering, Yuan Ze University, Taiwan.
     
  • February 2005 - July 2005, Tutor (Teaching Assistant) for the course of Digital System Design I,
    School of Information Technology & Electrical Engineering, The University of Queensland, Australia.
     
  • July 2004 - November 2004, Tutor (Teaching Assistant) for the course of Digital System Design II,
    School of Information Technology & Electrical Engineering, The University of Queensland, Australia.
     
  • July 1999 - April 2002, Software Engineer, R&D of Hercules/Venus,
    Avant! Corporation (merged by Synopsys), Taipei, Taiwan.
     
  • 1995 - 1996, Intern of Software Engineer,
    Institute for Information Industry, Taipei, Taiwan.
       
Research Grants
  • August 2013 - July 2014, A Parallel Software System for Parameterized Layout Design and Circuit Extraction II (含參數佈局圖設計與電路萃取之平行化軟體系統 II), National Science Council, Taiwan.  [NSC-102-2221-E-155-088]
  • August 2012 - July 2013, A Parallel Software System for Parameterized Layout Design and Circuit Extraction I (含參數佈局圖設計與電路萃取之平行化軟體系統 I), National Science Council, Taiwan.  [NSC-101-2221-E-155-074]
  • August 2010 - July 2011, A Study on Parallel Computing for Analog Layout Design Automation (以平行化計算方法應用於類比積體電路佈局圖設計自動化), National Science Council, Taiwan.  [NSC-99-2221-E-155-088]
  • August 2009 - July 2010, A Study on the Reduction of Re-design Iterations in Analog Integrated Circuit Design (類比積體電路重複設計次數降低之研究), National Science Council, Taiwan.  [NSC-98-2221-E-155-053]
Other Grants
  • July 2012 - January 2014, 教育部智慧電子跨領域應用專題系列課程計畫「車用電子系統」
  • July 2012 - February 2013, 指導大專生國科會計畫「以平行化演算法在分散式系統上切割含參數多邊形」
  • January 2012 - October 2012, 元智大學101學年度教學卓越計畫-「單晶片系統與嵌入式系統之實作與設計自動化」子計畫-主持人
  • August 2010 - July 2011, 教育部顧問室「前瞻晶片系統設計(SoC)學程計畫」(99 學年度)
  • August 2009 - July 2010, 教育部顧問室「前瞻晶片系統設計(SoC)學程計畫」(98 學年度)
Training
  • August 8, 2011 - August 19, 2011, Faculty Development Program, The University of New South Wales, Australia
Honors & Awards
  • Bright Idea Award (with other colleagues) in the 2013 R&D Idea Forum at TSMC.
  • Teaching Contribution Award in 2012, Yuan Ze University, Taiwan.
  • The Award of Advising Students Winning the 2nd Place (Top 3) in the 2012 CAD (Computer-Aided Design) Contest, Ministry of Education, Taiwan.
  • September 2012 - August 2015, Alumni Committee of National Tsing Hua University (國立清華大學校友會 - 第四屆校友會會員代表).
  • 2008, Who's Who in the World (2009 Edition).
  • 2007, Marquis Who's Who in Science and Engineering (10th Anniversary Edition, 2008-2009).
  • August 2005 - April 2007, University of Queensland Confirmation Scholarship (UQCS) (AU$18,837 per annum).
  • October 2003 - August 2005, ITEE International Scholarship, The University of Queensland (AU$11,115 per annum).
  • 2003, Member, Chinese Tai-Chi Institute, Taipei, Taiwan.
  • 1994, Yo-Shyang Scholarship, Yuan Ze University, Taiwan.
Professional Services
Memberships
  • August 2012-Present, Member of TICD (Taiwan IC Design Society)
  • May 2007-Present, Associate Member of Free Software Foundation
  • April 2004-Present, Member of ACM (Lifetime Membership)
  • 2004-Present, Member of ACM SIGDA
  • August 2010-Present, Member of IAENG (International Association of Engineers)
  • April 2004-Present, Member of IEEE
Projects
  • March 2005-2008, OwlVision GDSII Viewer
    OwlVision is a free software project aimed at developing a GDSII viewer by using Java programming language. OwlVision has GUI interface written by Java Swing/AWT and built-in translators written by Java compiler-compiler (JavaCC). The source code can be downloaded from http://www.owlvision.org.

Presentations
  • June 18, 2013,
    Fast Partitioning of Parameterized 45-Degree Polygons into Parameterized Trapezoids,” IEEE International New Circuits and Systems Conference (NEWCAS), Paris, France.
  • March 6, 2013,
    Relocatable and Resizable SRAM Synthesis for Via Configurable Structured ASIC, Session 4C, IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, California, USA.
  • November 23, 2011,
    “Solving VLSI Routing Problems with Optimization Tools,” Seminar for postgraduate students, Department of Computer Science, Taipei Municipal University of Education (TMUE), Taiwan.
  • October 28, 2011,
    元智大學資訊工程系簡介, 桃園縣立大園國際高級中學(大園高中), Taiwan.
  • October 17, 2011,
    “Solving VLSI Routing Problems with Optimization Tools,” Seminar for postgraduate students, Department of Electronic Engineering, National Taiwan University of Science and Technology (NTUST), Taiwan.
  • July 21, 2011,
    “Dogleg Channel Routing with Parallel Mixed Integer Linear Programming Solvers,” Worldcomp-PDPTA-2011, Las Vegas, Nevada, USA.
  • November 24, 2010,
    Efficient Partitioning of Parameterized 45-Degree Polygons with Mixed ILP,” TENCON-2010, Fukuoka, Japan.
  • November 1, 2010,
    Obstacle-Avoiding Switchbox Routing with CP and Parallel MILP,” ADPC-2010, Singapore.
  • July 13, 2010,
    “Constraint-Based Dogleg Channel Routing with Via Minimization,” Worldcomp-ICAI-2010, Las Vegas, Nevada, USA.
  • December 2009,
    “Decomposition of Parameterized Orthogonal Polygons via Formal Transformations,”
    ICDC-2009, Taiwan.
  • June 19, 2009,
    “Estimation of Analog Layout Parasitics with Parameterized Polygons,” EDA Forum & Industrial-Academic Panel, NCTU, Taiwan.
  • October 29, 2008,
    元智大學資訊工程系簡介, 國立清水高中, Taiwan.
  • January 27, 2005,
    Automation of Layout-Aware Analog Integrated Circuit Design,” Ph.D. Confirmation Seminar, School of ITEE, The University of Queensland, Australia.
  • October 2004,
    A Layout-Aware Circuit Sizing Model Using Parametric Analysis,” SASIMI-2004, Kanazawa, Japan.
Services at YZU
  • August 2011 - February 2012,
    元智資工系學系導師
  • August 2008 - July 2012,
    元智資工碩士班口試委員
  • 2010-2011,
    元智資工碩士班入學考試命題委員
  • March 13, 2010 - July 31, 2013,
    元智資工系友會總幹事
  • 2010,
    經典大使審查委員
  • August 2008 - July 2012,
    元智大學資訊工程系大學部招生委員會 (97-100 學年度)

last update: February 15, 2014