CS204B - Digital System Design
(數位系統設計)

Department of Computer Science & Engineering
Yuan Ze University

Instructor

Textbook

References

Grading Policy

Teaching Assistant

Venue

Time

Timetable (tentative and subject to change)

Week

 Date
(2009-2010)

Topics

 Reading Homework　
1 9/10
(Thu.)

Syllabus
Ch01: Introduction (About Digital Design, Analog vs. Digital, Digital Devices, Electronic Aspects of Digital Design, Software Aspects of Digital Design, Integrated Circuits)

 1.1 ~ 1.6  
2 9/16
(Wed.)

Ch01: Introduction (Integrated Circuits, PLD, ASIC, PCB, etc.)
Ch02: Number Systems and Codes

 1.6 ~ 1.12  
9/17
(Thu.)

Ch02: Number Systems and Codes (Positional Number Systems, Octal and Hexadecimal Numbers, General Positional-Number-System Conversions)

 2.1 ~ 2.3  
3 9/23
(Wed.)

Ch02: Number Systems and Codes (General Positional-Number-System Conversions, Addition and Subtraction of Non-decimal Numbers)

 2.3 ~ 2.4
9/24
(Thu.)

Ch02: Number Systems and Codes (Addition and Subtraction of Non-decimal Numbers, Signed-Magnitude Rep., One's Complement Rep., Two's Complement Rep.)

 2.4 ~ 2.5  
4 9/30
(Wed.)

Ch02: Number Systems and Codes (Two's Complement Rep., Two's-Complement Addition and Subtraction, Overflow)

 2.5 ~ 2.6  
10/1
(Thu.)		 Ch02: Number Systems and Codes 2.6, 2.10, 2.11, 2.12, 2.13  
5 10/7
(Wed.)		 Ch03: Digital Circuits (Logic Gates, Truth Tables) 3.1 ~ 3.3
  • Deadline of HW #1
  • HW #2
10/8
(Thu.)		 Ch03: Digital Circuits (CMOS Logic, Electrical Behavior of CMOS Circuits) 3.3 ~ 3.4  
6 10/14
(Wed.)		 Ch03: Digital Circuits (Electrical Behavior of CMOS Circuits, CMOS Static Electrical Behavior) 3.4 ~ 3.5  
10/15
(Thu.)		 Ch03: Digital Circuits (CMOS Static Electrical Behavior) 3.5
  • Deadline of HW #2
7 10/21
(Wed.)		 Ch03: Digital Circuits (CMOS Static Electrical Behavior) 3.5
10/22
(Thu.)		 Ch04: Combinational Logic Design Principles (Switching Algebra) 4.1  
8 10/28
(Wed.)		 Ch04: Combinational Logic Design Principles (Switching Algebra, Combinational-Circuit Analysis) 4.1 ~ 4.2  
10/29
(Thu.)		 Ch04: Combinational Logic Design Principles (Combinational-Circuit Synthesis, Karnaugh Maps) 4.3
  • Deadline of HW #3
9 11/4
(Wed.)		 Ch04: Combinational Logic Design Principles (Combinational-Circuit Synthesis, Karnaugh Maps) 4.3  
11/5
(Thu.)		 數位系統設計-期中考

期中考考試時間: 11月5日 (14:10 - 16:00) 請提早十分鐘到達考場

期中考考試地點: 1401B 教室

注意： 必須攜帶學生證應考，考試時手機請關機(手機開震動還是會有聲音)，不得攜帶計算機、字典、電子字典、任何書籍或紙張。

注意： 完成考試的同學請盡速離開考場，並且勿在考場附近逗留或大聲喧嘩。影響他人考試者將扣期中考分數。

(期中考週：11月5日~11月11日)		    
10 11/11
(Wed.)		 停課一次
(期中考週：11月5日~11月11日)		    
11/12
(Thu.)		 檢討期中考考卷
Ch04: Combinational Logic Design Principles (Combinational-Circuit Synthesis, Karnaugh Maps)
Ch05: Hardware Description Languages		 4.3,
5.1
11 11/18
(Wed.)		 全校運動會 - 停課一次    
11/19
(Thu.)		 Ch05: Hardware Description Languages (including Verilog)
Ch06: Combinational Logic Design Practices (including Decoders)		 5.1, 5.4,
6.4
  • Deadline of HW #4
12 11/25
(Wed.)		 Ch06: Combinational Logic Design Practices (including Decoders) 6.4  
11/26
(Thu.)		 Ch06: Combinational Logic Design Practices (including Encoders, Three-State Devices, Multiplexers, Exclusive-OR Gates, Parity Circuits) 6.5 ~ 6.8  
13 12/2
(Wed.)		 Ch06: Combinational Logic Design Practices (including Exclusive-OR Gates, Parity Circuits, Comparators, Adders) 6.8 ~ 6.10

 
12/3
(Thu.)		 Ch06: Combinational Logic Design Practices (including Adders, ALUs)
Ch07: Sequential Logic Design Principles (including S-R Latch)		 6.10,
7.1 ~ 7.2
14 12/9
(Wed.)		 Ch07: Sequential Logic Design Principles (including S'-R' Latch, D Latch, D Flip-Flop) 7.2
12/10
(Thu.)		 Ch07: Sequential Logic Design Principles(including D Flip-Flop) 7.2
  • Deadline of HW #5
15 12/16
(Wed.)		 Ch07: Sequential Logic Design Principles (including Clocked Synchronous State-Machine Analysis) 7.2 ~ 7.3
12/17
(Thu.)		 因舉辦 ICDC-2009 會議，所以停課一次  
  • Deadline of HW #6
16 12/23
(Wed.)		 Ch07: Sequential Logic Design Principles (including Clocked Synchronous State-Machine Design) 7.4  
12/24
(Thu.)		 Ch07: Sequential Logic Design Principles (including Clocked Synchronous State-Machine Design) 7.4  
17 12/30
(Wed.)		 Ch07: Sequential Logic Design Principles (including Clocked Synchronous State-Machine Design, J-K Flip-Flop, T Flip-Flop)
Ch08: Sequential Logic Design Practices		 7.2 7.4, 7.13, and
8.4		    
12/31
(Thu.)		 Ch08: Sequential Logic Design Practices (including Counters, Shift Registers, and Clock Skew)
總複習 (講解971學期數位系統設計期末考考卷)		 8.4, 8.5, and 8.8
  • Deadline of HW #7 (extended)
  • HW #8
18 1/6
(Wed.)		 總複習  
  • Deadline of HW #8
1/7
(Thu.)		 數位系統設計-期末考

期末考考試時間: 1月7日 (14:10 - 16:00) 請提早十分鐘到達考場

期末考考試地點: 1401B 與 1204 教室

注意：必須攜帶學生證應考，考試時手機請關機(手機開震動還是會有聲音)，不得攜帶計算機、字典、電子字典、任何書籍或紙張。

注意：完成考試的同學請盡速離開考場，並且勿在考場附近逗留或大聲喧嘩。影響他人考試者將扣期末考分數。

(期末考週：1月7日~13日)		    
19 1/13
(Wed.)		 課程結束
(期末考週：1月7日~13日)		 　 　

 

last update: January 11, 2010