Autumn 2010 (99-1
學期)
Department of Computer Science & Engineering
Yuan Ze University
Instructor
Textbook
References
Grading Policy
Teaching Assistant
Venue
Lecture Time
Timetable (tentative and subject to change)
|
Week |
Date (2010-2011) |
Topics |
Reading | Homework |
| 1 | 9/09 (Thu.) |
Syllabus |
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| 2 | 9/15 (Wed.) |
Ch01: Introduction (incl. About Digital Design, Analog vs. Digital, Digital Devices, Logic Gates) | 1.1 ~ 1.4 |
|
| 9/16 (Thu.) |
Ch01: Introduction (inc. Electronic Aspects of Digital Design, Software Aspects of Digital Design, Integrated Circuits, PLD, ASIC, PCB, The Name of the Game) |
1.5 ~ 1.11 | ||
| 3 | 9/22 (Wed.) |
中秋節放假一天 | ||
| 9/23 (Thu.) |
Ch02: Number Systems and Codes (incl. Positional Number Systems, Octal and Hexadecimal Numbers, General Positional-Number-System Conversions) |
2.1 ~ 2.3 |
|
|
| 4 | 9/29 (Wed.) |
Ch02: Number Systems and Codes (incl. General Positional-Number-System Conversions, Addition and Subtraction of Non-decimal Numbers) |
2.3 ~ 2.4 |
|
| 9/30 (Thu.) |
Ch02: Number Systems and Codes (incl. Signed-Magnitude Rep., One's Complement Rep., Two's Complement Rep.) | 2.5 | ||
| 5 | 10/06 (Wed.) |
Ch02: Number Systems and Codes (incl. Two's-Complement Addition and Subtraction, Overflow) | 2.6 |
|
| 10/07 (Thu.) |
Ch02: Number Systems and Codes (incl. Binary Codes for
Decimal Numbers, Gray Code, ASCII, Codes for States) Ch03: Digital Circuits (incl. Logic Gates, Truth Tables) |
2.10 ~ 2.13, 3.1 |
|
|
| 6 | 10/13 (Wed.) |
Ch03: Digital Circuits (incl. Logic Families, CMOS Logic) | 3.1 ~ 3.3 | |
| 10/14 (Thu.) |
Ch03: Digital Circuits (incl. CMOS Logic) | 3.3 |
|
|
| 7 | 10/20 (Wed.) |
老師請病假 補課方式：星期四的課提早十分鐘上課，而且下課時間縮短為 5 分鐘 |
|
|
| 10/21 (Thu.) |
Ch03: Digital Circuits (incl. Electrical Behavior of CMOS Circuits, Data Sheets, CMOS Static Electrical Behavior) | 3.4 ~ 3.5 | ||
| 8 | 10/27 (Wed.) |
Ch03: Digital Circuits (incl. CMOS Static Electrical Behavior) | 3.5 |
|
| 10/28 (Thu.) |
Ch03: Digital Circuits (incl. CMOS
Static Electrical Behavior, Transition Time, Propagation Delay, CMOS
Logic Families) Ch04: Combinational Logic Design Principles (incl. Switching Algebra) [The class starts at 1:00pm, instead of 1:10pm.] |
3.5, 3.6, 3.8, 4.1 |
||
| 9 | 11/03 (Wed.) |
張燿麟助教代課 (老師出國發表論文) Karnaugh Maps 介紹 |
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| 11/04 (Thu.) |
數位系統設計-期中考 考試時間: 11月4日 (13:10 - 15:00) 請提早十分鐘到達考場 考試地點: 1102 或 1016 教室 注意：必須攜帶學生證應考，考試時手機請關機(手機開震動還是會有聲音)，不得攜帶計算機、字典、電子字典、任何書籍或紙張。 注意：完成考試的同學請盡速離開考場，並且勿在考場附近逗留或大聲喧嘩。影響他人考試者將扣平時成績。 (期中考週：11月4日~11月10日) |
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| 10 | 11/10 (Wed.) |
期中考週停課一次 (期中考週：11月4日~11月10日) |
||
| 11/11 (Thu.) |
Ch04: Combinational Logic Design Principles (incl.
Switching Algebra) [The class starts at 1:00pm, instead of 1:10pm.] |
4.1 |
|
|
| 11 | 11/17 (Wed.) |
Prof. Yuan Xie (from PSU/NTHU) 來訪，停課一次 | 4.1 ~ 4.2 | |
| 11/18 (Thu.) |
Ch04: Combinational Logic Design Principles
(incl. Combinational-Circuit Synthesis, Karnaugh Maps) |
4.2 ~ 4.3 |
|
|
| 12 | 11/24 (Wed.) |
全校運動會，停課一次 | ||
| 11/25 (Thu.) |
老師請假一次
(參加 TENCON-2010 會議) 助教代課 (講解 Verilog) |
|
||
| 13 | 12/01 (Wed.) |
Ch04: Combinational Logic Design Principles (incl. Karnaugh Maps) | 4.3, Min.2 |
|
| 12/02 (Thu.) |
Ch05: Hardware Description Languages (incl. Verilog) Ch06: Combinational Logic Design Practices (incl. Decoders) |
5.1, 6.4 |
||
| 14 | 12/08 (Wed.) |
Ch06: Combinational Logic Design Practices (incl.
Decoders, Encoders) |
6.4 ~ 6.5 |
|
| 12/09 (Thu.) |
Ch06: Combinational Logic Design Practices (incl.
Encoders, Three-State Devices, Multiplexers, Exclusive-OR Gates, Parity
Circuits) |
6.5 ~ 6.8 | ||
| 15 | 12/15 (Wed.) |
Ch06: Combinational Logic Design Practices (incl. Parity Circuits, Comparators, Adders) |
6.8 ~ 6.10 |
|
| 12/16 (Thu.) |
Ch06: Combinational Logic Design Practices (incl.
Adders, ALUs) Extra: Universal Gates Ch07: Sequential Logic Design Principles (incl. S-R Latch) |
6.10, 7.1 ~ 7.2 |
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| 16 | 12/22 (Wed.) |
Ch07: Sequential Logic Design Principles (including
S'-R' Latch, S-R Latch with Enable, D Latch) |
7.2 |
|
| 12/23 (Thu.) |
Ch07: Sequential Logic Design Principles(incl. D Flip-Flop, J-K Flip-Flop, T Flip-Flop, Clocked Synchronous State-Machine Analysis) | 7.2 ~ 7.3 |
|
|
| 17 | 12/29 (Wed.) |
Ch07: Sequential Logic Design Principles (incl. Clocked Synchronous State-Machine Analysis) | 7.3 | |
| 12/30 (Thu.) |
Ch07: Sequential Logic Design Principles (incl. Clocked Synchronous State-Machine Design) | 7.4 |
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|
| 18 |
1/05 (Wed.) |
Review 總複習 (講解971~981學期數位系統設計期末考考卷) |
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1/06 (Thu.) |
數位系統設計-期末考 考試時間： 1月6日 (13:10 - 15:00) 請提早十分鐘到達考場 考試地點： 1016 與 1102 教室 考試範圍： Chapters 1-7 注意：必須攜帶學生證應考，考試時手機請關機(手機開震動還是會有聲音)，不得攜帶計算機、字典、電子字典、任何書籍或紙張。 注意：完成考試的同學請盡速離開考場，並且勿在考場附近逗留或大聲喧嘩。影響他人考試者將扣平時分數。 (期末考週：1月6日~12日) |
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| 19 | 1/12 (Wed.) |
課程結束 (期末考週：1月6日~12日) |
last update: January 04, 2011