CS204B - Digital System Design
(數位系統設計)

Autumn 2011  (100-1 學期)
Department of Computer Science & Engineering
Yuan Ze University

Instructor

Textbook

References

Grading Policy

Teaching Assistant

Venue

Lecture Time

Timetable (tentative and subject to change)

Week

 Date
(2011-2012)

Topics

 Coverage Homework　
1 9/07
(Wed.)

Syllabus

    
9/08
(Thu.)		 Ch01: Introduction (incl. About Digital Design, Analog vs. Digital, Digital Devices, Logic Gates, Electronic Aspects of Digital Design, Software Aspects of Digital Design, Integrated Circuits, PLD, ASIC, PCB, The Name of the Game) 1.1 ~ 1.11  
2 9/14
(Wed.)		 Ch02: Number Systems and Codes (incl. Positional Number Systems, Octal and Hexadecimal Numbers) 2.1 ~ 2.2
  • HW-01
9/15
(Thu.)

Ch02: Number Systems and Codes (incl. Octal and Hexadecimal Numbers, General Positional-Number-System Conversions, Addition and Subtraction of Non-decimal Numbers)

 2.2 ~ 2.4  
3 9/21
(Wed.)		 Ch02: Number Systems and Codes (incl. Addition and Subtraction of Non-decimal Numbers, and Signed-Magnitude Rep.) 2.4 ~ 2.5
  • Deadline of HW-01
9/22
(Thu.)

Quiz #1 (Sections 1.1~2.3)
Solving Quiz #1 Questions
Ch02: Number Systems and Codes (incl. Signed-Magnitude Rep., One's Complement Rep.)

 2.5

 
4 9/28
(Wed.)

Ch02: Number Systems and Codes (incl. Two's Complement Rep.)

 2.5

 
9/29
(Thu.)		 Ch02: Number Systems and Codes (incl. Two's-Complement Addition and Subtraction, Overflow)
Ch04: Combinational Logic Design Principles (incl. Switching Algebra, Inverter, AND gate, OR gate)		 2.6,
4.1		  
5 10/05
(Wed.)		 Ch02: Number Systems and Codes (incl. Binary Codes for Decimal Numbers) 2.10

 
10/06
(Thu.)		 Quiz #2 (Sections 2.4~2.6)
Solving Quiz #2 Questions
Ch02: Number Systems and Codes (incl. Binary Codes for Decimal Numbers, Gray Code)
 2.10 ~ 2.11

 
6 10/12
(Wed.)		 Ch02: Number Systems and Codes (incl. Gray Code, ASCII, Codes for States)
Ch04: Combinational Logic Design Principles (incl. Switching Algebra)		 2.11 ~ 2.13,
4.1		  
10/13
(Thu.)		 Ch04: Combinational Logic Design Principles (incl. Switching Algebra, DeMorgan's Theorems, Truth Table, SOP, POS, Minterms, Maxterms) 4.1

 
7 10/19
(Wed.)		 Ch04: Combinational Logic Design Principles (incl. Standard Representations of Logic Functions) 4.1

 
10/20
(Thu.)		 Quiz #3 (Sections 2.10~2.13)
Solving Quiz #3 Questions
Ch04: Combinational Logic Design Principles (incl. Combinational-Circuit Analysis, Combinational-Circuit Synthesis)		 4.2 ~ 4.3
  
8 10/26
(Wed.)		 Ch04: Combinational Logic Design Principles (incl. Combinational-Circuit Synthesis, Karnaugh Maps)
 4.3

 
10/27
(Thu.)		 Ch04: Combinational Logic Design Principles (incl. Karnaugh Maps, Prime Implicants, Karnaugh Maps with Don't Cares, 5-Variable Karnaugh Maps)
考前複習		 4.3,
Min.pdf		  
9 11/02
(Wed.)		 期中考週停課一次
(期中考週：10月31日~11月04日)		    
11/03
(Thu.)

Midterm Exam (數位系統設計 - 期中考)

Exam Date and Time (考試時間): 11月3日 (10:10am ~ 12:00pm) 請提早十分鐘到達考場

Location (考試地點): 1202 或 1204 教室

Coverage: Chapter 1 (including Sections 1.1~1.12), Chapter 2 (including Sections 2.1~2.6 and 2.10~2.13), and Chapter 4 (including Sections 4.1~4.3)

Note: Please bring your student ID. Please turn off your mobile phone(s) while taking the exam. Please do not bring/take/use any calculators, dictionaries, electronic dictionaries, laptop computers, tablet computers, books, or pieces of papers while taking the exam.

Note: After taking the exam, please quietly leave the classroom and do not wander or talk near the classroom.

注意：必須攜帶學生證應考，考試時手機請關機(手機開震動還是會有聲音)，不得攜帶計算機、字典、電子字典、筆記型電腦、平板電腦、任何書籍或紙張。

注意：完成考試的同學請盡速並安靜地離開考場，並且勿在考場附近逗留或大聲談話/喧嘩。影響他人考試者將扣期中考分數或平時分數。

(The week for midterm exams: 10/31~11/04)

    
10 11/09
(Wed.)		 Solving Questions in the Midterm Exam
Ch04: Combinational Logic Design Principles (incl. Karnaugh Maps)
 4.3  
11/10
(Thu.)		 Extra: Universal Gates (NAND and NOR)
Ch05: Hardware Description Languages (incl. Verilog)
Ch06: Combinational Logic Design Practices (incl. Decoders)		 5.1,
6.4

 
11 11/16
(Wed.)		 Ch06: Combinational Logic Design Practices (incl. Decoders, Verilog Code for Decoders)
 6.4  
11/17
(Thu.)		 Ch06: Combinational Logic Design Practices (incl. Decoders, Verilog Code for Decoders, Encoders, Verilog Code for Encoders, Three-State Devices, Verilog Code for Three-State Devices, Multiplexers, Verilog Code for Multiplexers, XOR, XNOR)
 6.4 ~ 6.8  
12 11/23
(Wed.)		 校運會（全校停課）    
11/24
(Thu.)		 Ch06: Combinational Logic Design Practices (incl. XOR, XNOR, Parity Circuits, Comparators, Adders, ALUs) 6.8 ~ 6.10

 
13 11/30
(Wed.)		 Quiz #4 (Sections 4.1~4.3, Universal Gates, Sections 6.4)
Solving Quiz #4 Questions		  

 
12/01
(Thu.)		 Ch07: Sequential Logic Design Principles (including Bistable Elements, S-R Latch, Propagation Delay Time, Rise Time, Fall Time, Hold Time)
 7.1 ~ 7.2
  
14 12/07
(Wed.)		 Ch07: Sequential Logic Design Principles(incl. , S'-R' Latch, S-R Latch with Enable, D Latch, Setup Time, Hold Time)
 7.2

 
12/08
(Thu.)		 Ch07: Sequential Logic Design Principles (incl. D Latch, D Flip-Flop, Clocked Synchronous State-Machine Analysis)
 7.2 ~ 7.3  
15 12/14
(Wed.)		 Ch07: Sequential Logic Design Principles (incl. Clocked Synchronous State-Machine Analysis - More Examples)
 7.3

 
12/15
(Thu.)		 Quiz #5 (Sections 6.4~6.7)
Solving Quiz #5 Questions
Ch07: Sequential Logic Design Principles (incl. J-K Flip-Flop, T Flip-Flop, Clocked Synchronous State-Machine Design)
 7.2,
7.4
  
16 12/21
(Wed.)		 Ch07: Sequential Logic Design Principles (incl. Clocked Synchronous State-Machine Design)
 7.4

 
12/22
(Thu.)		 Quiz #6 (Sections 7.1~7.3)
Solving Quiz #6 Questions
Ch03: Digital Circuits (incl. Logic Gates, Truth Tables, Logic Families, CMOS Logic, CMOS Inverter)		 3.1 ~ 3.3

 
17 12/28
(Wed.)		 Ch03: Digital Circuits (incl. CMOS Logic, Electrical Behavior of CMOS Circuits, Data Sheets) 3.3 ~ 3.4    
12/29
(Thu.)		 Quiz #7 (Section 7.4)
Solving Quiz #7 Questions
Ch03: Digital Circuits (incl. Electrical Behavior of CMOS Circuits, CMOS Static Electrical Behavior, Logic Levels, Fan-In, Fan-Out, CMOS Dynamic Electrical Behavior, Transition Time, Rise Time, Fall Time, Propagation Delay, CMOS Logic Families)		 3.4 ~ 3.6, 3.8

 
18 1/04
(Wed.)		 不需要上課
(期末考週：1月2日~6日)		  

 
1/05
(Thu.)		 數位系統設計-期末考

考試時間： 1月5日 (10:10am ~ 12:00pm) 請提早十分鐘到達考場

考試地點： 1202 與 1204 教室

考試範圍： Chapters 1-7, and Universal Gates

注意：必須攜帶學生證應考，考試時手機請關機(手機開震動還是會有聲音)，不得攜帶計算機、字典、電子字典、任何書籍、或任何紙張。

注意：完成考試的同學請盡速離開考場，並且勿在考場附近逗留或大聲喧嘩。影響他人考試者將扣平時分數。

(期末考週：1月2日~6日)		    
19 1/11
(Wed.)		 課程結束
(期末考週：1月2日~6日)		 　 　
1/12
(Thu.)		      

     

last update: January 04, 2012