CS378A - Introduction to VLSI Design (超大型積體電路設計導論)
CS658A - VLSI Design (超大型積體電路設計)

Autumn 2011  (100-1 學期)
Department of Computer Science & Engineering
Yuan Ze University

Instructor

Textbook

References

Grading Policy

Teaching Assistant

Venue

Timetable (subject to change)

Week

 Date
(2011-2012)

Topics

 Reading Lab Homework　
1 9/06
(Tue.)		 Syllabus
Ch01: Introduction, n-type semiconductor, p-type semiconductor, p-n junction, diodes, and MOS Transistors		 1.1 ~ 1.3       
2 9/13
(Tue.)		 Ch01: MOS Transistors and CMOS Logic (incl. Inverter, NAND, NOR) 1.3 ~ 1.4

   

   
3 9/19
(Mon.)		 Tutorial #1
(19:00~21:00 at 1301A, TA:曾耀億)		   Tutorial-01
  • HW-1
  • HW-2
9/20
(Tue.)		 Ch01: CMOS Logic (incl. NOR, Compound Gates, Pass Transistors, Transmission Gates, Tristate Inverters, Tristate Buffers, Multiplexers) 1.4

Tutorial-01
9/20
(Tue.)		 Tutorial #1
(19:00~21:00 at 1301A, TA:張燿麟)		   Tutorial-01
4 9/27
(Tue.)		 Quiz #1
Solving Quiz #1 Questions
Ch01: CMOS Logic (incl. Multiplexers, Sequential Circuits)
Ch07: SPICE (incl. SPICE netlist format)
Tutorial #2		 1.4.8 ~ 1.4.9,
7.1 ~ 7.2		 Tutorial-02
  • Deadline of HW-1 (2011/09/30)
5 10/03
(Mon.)		 Tutorial #2
(19:00~21:00 at 1301A, TA:曾耀億)		   Tutorial-02
  • HW-3
10/04
(Tue.)		 Ch07: SPICE (incl. SPICE netlist format, PWL, PULSE, .TRAN, .MEASURE, propagation delay, rise time, fall time)
Tutorial #2
HW-03
Ch01: CMOS Fabrication and Layout (incl. Inverter Cross-Section)
 7.1 ~ 7.2,
1.5.1		 Tutorial-02
  • Deadline of HW-2 (2011/10/07)
10/04
(Tue.)		 Tutorial #2
(19:00~21:00 at 1301A, TA:張燿麟)		   Tutorial-02
  • Deadline of HW-2 (2011/10/07)
6 10/11
(Tue.)		 Ch01: CMOS Fabrication and Layout (incl. Fabrication Process, Layout, Layout Design Rules)
Ch15: Fabrication
 1.5,
15.1 ~ 15.2

    
  • Deadline of HW-3 (2011/10/14)
10/11
(Tue.)		 Lab. Exercises
(19:00~21:00 at 1301A, TA:張燿麟)		    
  • HW-4
7 10/17
(Mon.)		 Tutorial #3
Tutorial #4
(19:00~21:00 at 1301A, TA:曾耀億)		   Tutorial-03
Tutorial-04
  • HW-5
10/18
(Tue.)		 Ch01: CMOS Fabrication and Layout (incl. Layout Design Rules, Stick Diagrams)
 1.5.3, 1.5.4, 1.5.5

 
  • Deadline of HW-4 (2011/10/21)
10/18
(Tue.)		 Tutorial #3
Tutorial #4
(19:00~21:00 at 1301A, TA:張燿麟)		   Tutorial-03
Tutorial-04		  
8 10/25
(Tue.)

Quiz #2
Solving Quiz #2 Questions
Ch01: CMOS Fabrication and Layout (incl. Stick Diagrams, Stick_Diagram-to-Schematic Transformation)
Ch15: Fabrication (incl. Layout Design Rules, Active Region, p-select, n-select, Design Rule Checking)

 1.5.5,
15.3

  
  • Deadline of HW-5 (2011/10/28)
9 11/01
(Tue.)

Midterm Exam (Intro. to VLSI Design, VLSI Design)

Exam Date and Time: November 1 (Tuesday)  9:10am ~ 12:00pm (Please arrive at Classroom 1111 by 9:00am.)

Location: Classroom 1111

Coverage: The midterm exam will cover Chapter 1 (including Sections 1.1~1.5), Chapter 7 (including Sections 7.1~7.2), and Chapter 15 (including Sections 15.1~15.3) of the textbook.

Note: Please bring your student ID. Please turn off your mobile phone(s) while taking the exam. Please do not bring/take/use any calculators, dictionaries, electronic dictionaries, laptop computers, tablet computers, books, or pieces of papers while taking the exam.

Note: After taking the exam, please quietly leave the classroom and do not wander or talk near the classroom.

注意： 必須攜帶學生證應考，考試時手機請關機，不得攜帶計算機、字典、電子字典、筆記型電腦、平板電腦、任何書籍或紙張。

注意： 完成考試的同學請盡速並安靜地離開考場，並且勿在考場附近逗留或大聲喧嘩。影響他人考試者將扣期中考分數或平時分數。

(The week for midterm exams: 10/31~11/04)

      
10 11/08
(Tue.)

Ch01: CMOS Fabrication and Layout (incl. Stick Diagrams and Area Estimation)
Ch15: Fabrication (incl. Technology-related CAD Issues, Design Rule Checking, Mask Layer Operations, Circuit Extraction, Layout versus Schematic)
Ch11: Memories (incl. Introduction, SRAM)

 1.5.5,
15.5
11.1 ~ 11.2		  

 
11 11/15
(Tue.)		 教學卓越中心派人員錄影上課的過程
Ch11: Memories (incl. SRAM, SRAM Cells, Read and Write Operations of SRAM Cells)
 11.2  
  • HW-6
11/15
(Tue.)		 Quiz #3 (Group 1): Exam for Lab Exercises (上機考) - CS658A (postgraduate students)      
12 11/22
(Tue.)		 Quiz #4
Solving Quiz #4 Questions
Ch02: Devices (incl. Ideal I-V Characteristics of nMOS)		 2.1 ~ 2.2  

 
11/22
(Tue.)		 Quiz #3 (Group 2): Exam for Lab Exercises (上機考) - CS378A (undergraduate students)    
  • Deadline of HW-6 (2011/11/25)
  • HW-7
13 11/29
(Tue.)		 HW-6 and HW-7
Ch02: Devices (incl. Ideal I-V Characteristics of nMOS and pMOS)
Ch07: SPICE (incl. Transistor DC Analysis)
 11.2,
2.2,
7.2.2		  
  • Deadline of HW-6 (2011/11/25)
  • Project-1
11/29
(Tue.)		 Quiz #3 (Group 3): Exam for Lab Exercises (上機考) - CS378A (undergraduate students)    
  • Deadline of HW-7 (2011/12/02)
  • HW-8
14 12/06
(Tue.)		 Visit NDL/CIC in Hsin-Chu
(8:20am 在一館的郵局和提款機附近集合)
 
  • Deadline of HW-8 (2011/12/09)
15 12/13
(Tue.)		 Project-1 (Register File's Column Circuitry, Row Circuitry, Write Drivers)
Ch02: Devices (incl. C-V Characteristics, Nonideal I-V Effects, Leakage, DC Transfer Characteristics, Beta Ratio)
Ch11: Array Subsystems (incl. DRAM Cells)		 11.2,
2.3 ~ 2.5,
11.3,
  

 
12/13
(Tue.)		 課輔/補課 (7:00pm~9:00pm) @ 1401A
Ch02: Devices (incl. Beta Ratio, , Noise Margins, DC Transfer Characteristics, Pass Transistor DC Characteristics)
解考古題 (Pass Transistor DC Characteristics)
Ch03: Speed (incl. Propagation Delay, Contamination Delay, Rise Time, Fall Time, Edge Rate, Arrival Time, Slack, Capacitances for Inverter Delay Calculations)		 2.5 ~ 2.6,
3.1 ~ 3.2		    
16 12/20
(Tue.)		 Quiz #5 (Ch02)
Ch03: Speed (incl. Effective Resistance, Gate and Diffusion Capacitance, Equivalent RC Circuits, Inverter Delay Calculations, RC Delay Model, Elmore Delay, Delay Estimation)
 3.1 ~ 3.3
    
12/20
(Tue.)		 補課 (7:00pm~9:00pm) @ 1401A
Ch03: Speed (incl. RC Delay Model, Delay Estimation, Elmore Delay, Linear Delay Model, Logical Effort, Parasitic Delay, Electrical Effort)		 3.3 ~ 3.4    
17 12/27
(Tue.)		 Quiz #6 (Ch03: Sections 3.1~3.4)
Solving Quiz #6 Problems
Ch03: Speed (incl. Logical Effort of Paths, Choosing the Best Number of Stages)		 3.4 ~ 3.5  
  • Deadline of Project-1 (2011/12/28)
12/27
(Tue.)		 補課 (7:00pm~9:00pm) @ 1401A
Ch05: Wires (incl. Interconnect Modeling, pi-model, Crosstalk)
Ch04: Power (incl. Dynamic Power, Activity Factor, Voltage Domains, Dynamic Voltage Scaling, Static Power, Leakage, Power Gating)		 5.1 ~ 5.2,
4.1 ~ 4.3		    
18 1/03
(Tue.)		 Final Exam (VLSI Design/Intro. to VLSI Design)

Exam Date and Time: January 3rd (Tuesday) 09:10am - 12:00pm

Location: Classroom 1111

Coverage: The exam will cover Chapters 1, 2, 3, 4, 5, 7, 11, and 15.

注意： 可以攜帶本課程指定之教科書應考。
注意： 必須攜帶學生證應考，考試時手機請關機，不得攜帶計算機、字典、電子字典、教科書以外之任何書籍、或任何紙張。

注意： 完成考試的同學請盡速離開考場，並且勿在考場附近逗留或大聲喧嘩。影響他人考試者將扣期中考分數或平時分數。

(The week for final exams: 1/02~1/06)		      
19 1/10
(Tue.)		 課程結束      

       

last update: January 02, 2012