CS204B - Digital System Design
(數位系統設計)

Autumn 2012  (101-1 學期)
Department of Computer Science & Engineering
Yuan Ze University


Instructor

Textbook

References

Grading Policy

Teaching Assistant

Venue

Lecture Time


Timetable (tentative and subject to change)

Week

Date
(2012-2013)

Topics

Coverage Homework 
1 9/19
(Wed.)

Syllabus

   
9/20
(Thu.)
Syllabus
Introduction, Logic Gates, Truth Tables, Half Adder
   
2 9/26
(Wed.)
Half Adder, Full Adder, Binary Addition
 

   

9/27
(Thu.)
Full Adder, Ripple-Carry Adder
Ch01: Introduction (incl. About Digital Design, Analog vs. Digital, Digital Devices, Logic Gates, Electronic Aspects of Digital Design, Software Aspects of Digital Design, Integrated Circuits, PLD, FPGA, ASIC, PCB, The Name of the Game)
Ch01
  • HW-1
3 10/03
(Wed.)

Ch02: Number Systems and Codes (incl. Positional Number Systems, Decimal Numbers, Binary Numbers, Octal and Hexadecimal Numbers)

2.1 - 2.2
  • Deadline of HW-01
10/04
(Thu.)

Ch02: Number Systems and Codes (incl. Octal and Hexadecimal Numbers, General Positional-Number-System Conversions, Addition and Subtraction of Non-decimal Numbers)

2.2 - 2.4

 

4 10/10
(Wed.)
國慶日(放假一天)
Public Holiday
 

 

10/11
(Thu.)
(The class starts at 1:00pm)
Quiz #1 (Sections 1.1~2.3)
Ch02: Number Systems and Codes (incl.  Signed-Magnitude Rep., One's Complement Rep., Two's Complement Rep.)
2.5  
5 10/17
(Wed.)
Ch02: Number Systems and Codes (incl. Two's Complement Rep., Two's-Complement Addition and Subtraction, Overflow) 2.5 - 2.6

 

10/18
(Thu.)
(The class starts at 1:00pm)
Ch02: Number Systems and Codes (incl. Two's-Complement Addition and Subtraction, Excess Representations, Binary Codes for Decimal Numbers, BCD, Gray Code)
2.5.7,
2.6,
2.10 - 2.11

 

6 10/24
(Wed.)
Quiz #2 (Sections 2.1 - 2.6)
Ch02: Number Systems and Codes (incl. Gray Code, ASCII, Codes for States)
2.11 - 2.13  
10/25
(Thu.)
(The class starts at 1:00pm)
Ch04
: Combinational Logic Design Principles (incl. Switching Algebra, DeMorgan's Theorems, Duality)
4.1

 

7 10/31
(Wed.)
Ch04: Combinational Logic Design Principles (incl. Truth Tables, SOP, POS, Minterms, Maxterms, Standard Representations of Logic Functions) 4.1.6

 

11/01
(Thu.)
(The class starts at 1:00pm)
Ch04: Combinational Logic Design Principles (incl. Combinational-Circuit Analysis, Combinational-Circuit Synthesis)
4.2 - 4.3
 
8 11/07
(Wed.)
Ch04: Combinational Logic Design Principles (incl. Combinational-Circuit Synthesis, Karnaugh Maps)
4.3

 

11/08
(Thu.)
(The class starts at 1:00pm)
Ch04
: Combinational Logic Design Principles (incl. Karnaugh Maps, Distinguished 1-Cell, Prime Implicants)
4.3  
9 11/14
(Wed.)
期中考週停課一次
(期中考週:11月12日~11月17日)
   
11/15
(Thu.)

Midterm Exam (數位系統設計 - 期中考)

Exam Date and Time (考試時間): 1115 (Thursday) 13:10am ~ 15:00pm (請提早十分鐘到達考場)

Location (考試地點): 1401B 1111 教室

Coverage: Chapter 1 (including Sections 1.1~1.12), Chapter 2 (including Sections 2.1~2.6 and 2.10~2.13), and Chapter 4 (including Sections 4.1~4.3)

Note: Please bring your student ID. Please turn off your mobile phone(s) while taking the exam. Please do not bring/take/use any calculators, dictionaries, electronic dictionaries, laptop computers, tablet computers, electronic devices, books, or pieces of papers while taking the exam. After taking the exam, please quietly leave the classroom and do not wander or talk near the classroom.

注意:必須攜帶學生證應考,考試時手機請關機(手機開震動還是會有聲音),不得攜帶計算機、字典、電子字典、筆記型電腦、平板電腦、任何書籍或紙張。完成考試的同學請盡速並安靜地離開考場,並且勿在考場附近逗留或大聲談話/喧嘩。影響他人考試者將扣期中考分數或平時分數。

(The week for midterm exams: 11/12-11/17)

(期中考週:11月12日~11月17日)
   
10 11/21
(Wed.)
Ch04: Combinational Logic Design Principles (incl. Prime Implicants, Distinguished 1-Cells, Minimum SOP/POS Expressions, Karnaugh Maps, Don't Cares)
4.3,
Min.pdf
 
11/22
(Thu.)
(The class starts at 1:00pm)
Ch04: Combinational Logic Design Principles (incl. Karnaugh Maps with Don't Cares, 5-Variable Karnaugh Maps)
Extra: Universal Gates (NAND and NOR)
Ch05: Hardware Description Languages (incl. Verilog)
4.3,
Min.pdf,
5.1

 

11 11/28
(Wed.)
Ch05: Hardware Description Languages (incl. Verilog)
5.1  
11/29
(Thu.)
(The class starts at 1:00pm)
Quiz #3 (Chapter 4, Don't Cares, 5-Variable K-Maps, Universal Gates)
Ch06: Combinational Logic Design Practices (incl. Programmable Logic Arrays, Decoders, 2-to-4 Decoder, Verilog Code for 2-to-4 Decoder, 3-to-8 Decoder, 3-to-8 Decoder for Gray Code, BCD-to-7-Segment Decoder, Active Low, 74x138, Enable Signals, Verilog Code for 74x138-like Decoder, Truth Tables for Decoders)
6.3 - 6.4  
12 12/05
(Wed.)
Ch06: Combinational Logic Design Practices (incl. 5-to-32 Decoder, Encoders, Priority Encoders) 6.4 - 6.5  
12/06
(Thu.)
(The class starts at 1:00pm)
Ch06
: Combinational Logic Design Practices (incl. Decimal-to-BCD Encoder, 8-to-3 Encoder, 74x148, Verilog Code for 75x148-like Priority Encoder, Three-State Devices, Buffers & Inverters, 74x541, Verilog Code for 74x541-like Three-State Device, Multiplexers, 74x151, 74x157, Verilog Code for Multiplexers)
6.5 - 6.7

 

13 12/12
(Wed.)
Ch06: Combinational Logic Design Practices (incl. XOR, XNOR, Parity Circuits) 6.8
  • HW-2
12/13
(Thu.)
(The class starts at 1:00pm)
Ch06: Combinational Logic Design Practices (incl. Comparators, Adders, ALUs)
Ch07: Sequential Logic Design Principles (incl. Introduction, Bistable Elements, S-R Latch, Propagation Delay Time)
6.9 - 6.10,
7.1 - 7.2
 
14 12/19
(Wed.)
Solving Questions in Quiz-3
Ch07
: Sequential Logic Design Principles (incl. Propagation Delay Time, Rise Time, Fall Time, Minimum Pulse Width, S-R Latch, S'-R' Latch)
7.2
  • Deadline of HW-2
12/20
(Thu.)
(The class starts at 1:00pm)
Ch07
: Sequential Logic Design Principles (incl. S-R Latch with Enable, D Latch, Setup Time, Hold Time, D Latch, D Flip-Flop, Verilog Code for D Flip-Flops, J-K Flip-Flop)
7.2  
15 12/26
(Wed.)
Ch07: Sequential Logic Design Principles (incl. T Flip-Flop, T Flip-Flop with Enable, Clocked Synchronous State-Machine Analysis, Clocked Synchronous State-Machine Analysis - An Example)
7.2.11,
7.3

 

12/27
(Thu.)
(The class starts at 1:00pm)
Ch07: Sequential Logic Design Principles (incl. Clocked Synchronous State-Machine Analysis - An Example, Clocked Synchronous State-Machine Analysis - Another Example, Clocked Synchronous State-Machine Design - An Example)
7.3,
7.4
 
16 1/02
(Wed.)
Ch07: Sequential Logic Design Principles (incl. Clocked Synchronous State-Machine Design - An Example)
7.4

 

1/03
(Thu.)
(The class starts at 1:00pm)
Ch07: Sequential Logic Design Principles (incl. Verilog Code for State Machines, Clocked Synchronous State-Machine Design - Another Example)
Ch03: Digital Circuits (incl. Logic Gates, Truth Tables, Logic Families)
7.4,
3.1 - 3.3

 

17 1/09
(Wed.)
Ch03: Digital Circuits (incl. CMOS Logic, CMOS Inverter)
Quiz #4 (Sections 7.1-7.3)
3.3    
1/10
(Thu.)
(The class starts at 1:00pm)
Ch03: Digital Circuits (incl. CMOS Logic, CMOS NAND, CMOS NOR, AOI, OAI, Electrical Behavior of CMOS Circuits, Data Sheets, CMOS Static Electrical Behavior, Logic Levels, Noise Margins, Fan-In, Fan-Out, Circuit Behavior with Resistive Loads)
3.3 ~ 3.5

 

18 1/16
(Wed.)
不需要上課
(期末考週:1/14 - 1/19)
 

 

1/17
(Thu.)
數位系統設計-期末考

考試時間 1月17日 星期四 1:10pm - 3:00pm (請提早十分鐘到達考場)

考試地點 1401A 1401B 教室

考試範圍: Chapters 1-7, and Universal Gates

注意:必須攜帶學生證應考,考試時手機請關機(手機開震動還是會有聲音),不得攜帶計算機、字典、電子字典、任何書籍、或任何紙張。

注意
:完成考試的同學請盡速離開考場,並且勿在考場附近逗留或大聲喧嘩。影響他人考試者將扣平時分數。

(期末考週:1/14 - 1/19)
   
19 1/23
(Wed.)
課程結束    
1/24
(Thu.)
課程結束    

     


last update: February 03, 2013