CS378A - Introduction to VLSI Design (超大型積體電路設計導論)
CS658A - VLSI Design (超大型積體電路設計)

Autumn 2012  (101-1 學期)
Department of Computer Science & Engineering
Yuan Ze University

Instructor

Textbook

References

Grading Policy

Teaching Assistant

Venue

Timetable (subject to change)

Week

 Date
(2011-2012)

Topics

 Reading Lab Homework　
1 9/18
(Tue.)		 Syllabus           
2 9/25
(Tue.)		 Ch01: Introduction, n-type semiconductor, p-type semiconductor, p-n junction, diodes, and MOS Transistors (W, L, Circuit Symbols, Schematic, Layout, Polysilicon, Diffusion) 1.1 - 1.3

    

    

3 10/02
(Tue.)		 Ch01: Operations of MOS Transistors, MOS Transistors and CMOS Logic (incl. Inverter, NAND, NOR, Compound Gates) 1.4 (1.4.1 - 1.4.5)

    

     
4 10/09
(Tue.)		 Ch01: CMOS Logic (incl. Combinational Logic, Compound Gates, The Strength of a Signal, Pass Transistors, Transmission Gates, Buffer, AOI22 Gate)
Quiz #1		 1.4 (1.4.5 - 1.4.6)  
  • HW-1
5 10/16
(Tue.)		 Ch01: CMOS Logic (incl. Tristate Inverters, Tristate Buffers, 2:1 Multiplexers, 4:1 Multiplexers, D latches, D Flip-Flops)
Ch07: SPICE (incl. Introduction to Circuit Simulations and SPICE)
 1.4 (1.4.7 - 1.4.9),
7.1		  

 
10/15
(Mon.)		 Laboratory Exercise - Group 1
Tutorial #1
(18:30~21:20 at 1301A, TA:莊浚志)		 Tutorial #1
HW-1		  
  • HW-2
10/16
(Tue.)		 Laboratory Exercise - Group 2
Tutorial #1
(18:30~21:20 at 1301A, TA:張博超)		 Tutorial #1
HW-1		  
  • HW-2
10/17
(Wed.)		 Laboratory Exercise - Group 3
Tutorial #1
(18:30~21:20 at 1301A, TA:洪竣翔)		 Tutorial #1
HW-1		  
  • HW-2
6 10/23
(Tue.)		 Ch07: SPICE (incl. SPICE netlist format, RC Circuit Example, SPICE elements, PWL, PULSE, SUBCKT, .TRAN, Transient Analysis, Example in Tutorial-2) 7.2

    
  • Deadline of HW-1 (2012/10/26)
10/22
(Mon.)		 Laboratory Exercise - Group 1
(18:30~21:20 at 1301A, TA:莊浚志)		 Tutorial-1
HW-2		    
10/23
(Tue.)		 Laboratory Exercise - Group 2
(18:30~21:20 at 1301A, TA:張博超)		 Tutorial-1
HW-2		    
10/24
(Wed.)		 Laboratory Exercise - Group 3
(18:30~21:20 at 1301A, TA:洪竣翔)		 Tutorial-1
HW-2		  

 
7 10/30
(Tue.)		 Quiz #2 (Ch07, HSpice)
Ch07: SPICE (incl. .MEASURE, propagation delay, rise time, fall time)
Ch01: CMOS Fabrication and Layout (incl. Inverter Cross-Section, Inverter Layout)
 7.2,
1.5.1

 
  • Deadline of HW-2 (2012/11/02)
  • HW-3
  • HW-4
10/29
(Mon.)		 Laboratory Exercise - Group 1
(18:30~21:20 at 1301A, TA:莊浚志)		 Tutorial-2
HW-3		    
10/30
(Tue.)		 Laboratory Exercise - Group 2
(18:30~21:20 at 1301A, TA:張博超)		 Tutorial-2
HW-3		    
10/31
(Wed.)		 Laboratory Exercise - Group 3
(18:30~21:20 at 1301A, TA:洪竣翔)		 Tutorial-2
HW-3		    
8 11/06
(Tue.)

Ch01: Welcome to VLSI (incl. Fabrication Process, Layout, Photolithography)
Ch15: Fabrication (incl. Introduction, CMOS Technologies)
Silicon Run Video

 1.5.2,
15.1-15.2		  
  • Deadline of HW-3 (2012/11/09)
11/05
(Mon.)		 Laboratory Exercise - Group 1
(18:30~21:20 at 1301A, TA:莊浚志)		 HW-4    
11/06
(Tue.)		 Laboratory Exercise - Group 2
(18:30~21:20 at 1301A, TA:張博超)		 HW-4    
11/07
(Wed.)		 Laboratory Exercise - Group 3
(18:30~21:20 at 1301A, TA:洪竣翔)		 HW-4    
9 11/13
(Tue.)

Midterm Exam (Introduction to VLSI Design, VLSI Design)

Exam Date and Time: November 13 (Tuesday)  9:10am ~ 12:00pm (Please arrive at Lecture Hall on Level B1 of YZU Building #1 by 9:00am.)

Location: Lecture Hall on Level B1 of YZU Building #1

Coverage: The midterm exam will cover Chapter 1 (including Sections 1.1~1.5), Chapter 7 (including Sections 7.1~7.2), and Chapter 15 (including Sections 15.1~15.3) of the textbook.

Note: Please bring your student ID. Please turn off your mobile phone(s) while taking the exam. Please do not bring/take/use any calculators, dictionaries, electronic dictionaries, laptop computers, tablet computers, electronic devices, books, or pieces of papers while taking the exam. After taking the exam, please quietly leave the classroom and do not wander or talk near the classroom.

注意： 必須攜帶學生證應考，考試時手機請關機，不得攜帶計算機、字典、電子字典、筆記型電腦、平板電腦、電子產品、任何書籍或紙張。完成考試的同學請盡速並安靜地離開考場，並且勿在考場附近逗留或大聲喧嘩。影響他人考試者將扣平時分數。

(The week for midterm exams: 11/12~11/17)

      
10 11/20
(Tue.)

Ch01: CMOS Fabrication and Layout (incl. Layout Design Rules, MOSIS Design Rules)
Ch15: Fabrication (incl. Layout Design Rules, Active Region, p-select, n-select, Design Rule Checking)

 1.5.3,
15.3		  
  • Deadline of HW-4 (2012/11/23)
  • HW-5
11/19
(Mon.)		 Laboratory Exercise - Group 1
(18:30~21:20 at 1301A, TA:莊浚志)		 Tutorial-3 and Tutorial-4
HW-5		    
11/20
(Tue.)		 Laboratory Exercise - Group 2
(18:30~21:20 at 1301A, TA:張博超)		 Tutorial-3 and Tutorial-4
HW-5		    
11/21
(Wed.)		 Laboratory Exercise - Group 3
(18:30~21:20 at 1301A, TA:洪竣翔)		 Tutorial-3 and Tutorial-4
HW-5		    
11 11/27
(Tue.)		 Ch15: Fabrication (incl. Contact Rules, Via Rules, Summary of Design Rules)
Ch01: Welcome to VLSI (incl. Unit Transistor, Unit Inverter, Unit Inverter Layout, Stick Diagrams, Stick_Diagram-to-Schematic Transformation, Area Estimations with Stick Diagrams, Standard Cells, Standard Cell Library)
 15.3.1,
1.5.4 -  1.5.5,
1.10.2		  
12 12/04
(Tue.)		 Visit NDL (國家實驗研究院奈米元件實驗室) in Hsin-Chu
(8:20am 在一館的郵局和提款機附近集合)		    

 
13 12/11
(Tue.)		 Ch11: Memories (incl. Introduction, Categories of Memory Arrays, Memory Array Architecture, SRAM, SRAM Cells, Read and Write Operations of SRAM Cells)
 11.1 - 11.2  
  • HW-6
  • Project-1
14 12/18
(Tue.)		 Ch02: Devices (incl. Ideal I-V Characteristics of nMOS and pMOS, C-V Characteristics)
Ch07: SPICE (incl. Transistor DC Analysis)		 2.1 - 2.3,
7.2.2
  
  • Deadline of HW-6
15 12/25
(Tue.)		 Ch02: Devices (incl. Nonideal I-V Effects, Leakage, DC Transfer Characteristics, Beta Ratio, Pass Transistor DC Characteristics, Threshold Drop, Examples for Calculating Threshold Drops)
Ch03: Speed (incl. Propagation Delay, Contamination Delay, Rise Time, Fall Time, Edge Rate, Setup Time, Hold Time)		 2.3 - 2.6,
3.1		  
  • HW-7
  • Deadline of Project-1 (2012/12/28)
16 1/1
(Tue.)		 Public Holiday
 
  • Deadline of HW-7 (2013/01/04)
17 1/8
(Tue.)		 Ch03: Speed (incl. Setup Time, Hold Time, Arrival Time, Slack, Transient Response, Capacitances for Inverter Delay Calculations, Effective Resistance, Gate and Diffusion Capacitance, Equivalent RC Circuits, Inverter Delay Calculations, RC Delay Model, Elmore Delay, Delay Estimation) 3.1 - 3.3  

 
18 1/15
(Tue.)		 Final Exam (VLSI Design/Intro. to VLSI Design)

Exam Date and Time: January 15th (Tuesday) 10:10am - 12:00pm [請提早十分鐘到達考場]

Location: Classroom 60203 or 60205

Coverage: The exam will cover Chapters 1, 2, 3, 7, 11, and 15.

注意：必須攜帶學生證應考，考試時手機請關機(手機開震動還是會有聲音)，不得攜帶計算機、字典、電子字典、任何書籍、或任何紙張。

注意：完成考試的同學請盡速離開考場，並且勿在考場附近逗留或大聲喧嘩，影響他人考試者將扣平時分數。

(The week for final exams: 1/14 - 1/18)		      
19 1/22
(Tue.)		 課程結束      

       

last update: February 03, 2013