CS653 - Introduction to VLSI Design
(超大型積體電路設計導論)

Instructor

Textbook

References

Grading Policy

Teaching Assistant

Venue

Timetable (subject to change)

Week

 Date

Topics

 Reading Lab Homework　
1 ---- ---- ---- ---- ----
2 9/15
(Mon.)

問卷調查
Ch01: Introduction, MOS Transistors, and CMOS Logic

 1.1 ~ 1.4 ----
3 9/22
(Mon.)

Ch01: CMOS Logic, CMOS Fabrication and Layout

 1.4 ~ 1.5 Tutorial #1
4 9/29
(Mon.)

薔蜜颱風來襲，放假一天 (Typhoon Jangmi visited Taiwan)

 ---- ---- ----
5 10/6
(Mon.)

Ch03: CMOS Processing Technology,
Ch01: CMOS Fabrication and Layout, Stick Diagrams

 3.1 ~ 3.3, and
1.5		 Tutorial #2
6 10/13
(Mon.)		 Ch02: MOS Transistor Theory
10/8∼10/17 元智期初問卷調查
 2.1 ~ 2.7
(excluding 2.3.2, 2.3.3, and 2.5.4)		 ----
7 10/20
(Mon.)		 Ch05: Circuit Simulation (HSPICE)
10/8∼10/17 元智期初問卷調查		 5.1 ~ 5.3 Tutorial #3
  • Deadline of Practical #2
  • Deadline of Practical #3
  • Assignment #2
8 10/27
(Mon.)		 Ch03: Technology-related CAD Issues (DRC and Circuit Extraction),
Ch04: Circuit Characterization and Performance Estimation		 3.5, and
4.1 ~ 4.2		 　
9 11/3
(Mon.)		 Ch04: Circuit Characterization and Performance Estimation (including Logical Effort),
LE: Chapter 1 of the Logical Effort book		 4.2 ~ 4.3 (excluding 4.2.5) 　
10 11/10
(Mon.)		 Ch04: Logical Effort and Transistor Sizing,
LE: Chapters 1 and 2 of the Logical Effort book,
Ch01: Simple VLSI Design Flow
   
11/6~11/12 期中考週（須上課，上課時間和地點和平常相同）		 4.3 (excluding 4.3.6 and 4.3.7), and
1.9 ~ 1.11		 　
10 11/13
(Thu.)		 Tutorial #4
請到 1301A 上機使用 EDA 軟體
上課時間： 9:00am~10:00am		   Tutorial #4  
11 11/17
(Mon.)		 Ch06: Combinational Circuit Design (including Static CMOS, Ratioed Circuits, Cascode Voltage Switch Logic, and Dynamic Circuits) 6.1 ~ 6.2 　

  • Deadline of Assignment #4
12 11/24
(Mon.)		 Ch06: Combinational Circuit Design (Dynamic Circuits and Pass-transistor Circuits),
Ch04: Power Dissipation, Interconnect		 6.2, and
4.4 ~ 4.5		 　
  • Deadline of Assignment #5
13 12/1
(Mon.)		 Ch04: Interconnect, Wire Engineering,
Ch01: Latches and Flip-Flops,
Ch07: Sequential Circuit Design
Ch08: Design Methodology and Tools (including Design Economics)		 4.4 ~ 4.5,
1.4.9,
7.1, 7.3, and
8.5		 　
14 12/8
(Mon.)		 Ch08: Design Methodology and Tools (including Design Economics, Programmable Logic, and FPGA),
Appendix B: VHDL,
Ch01: Logic Design, Circuit Design		 8.5,
8.3.2,
Appendix B,
1.8, and
1.9		 　 　
15 12/15
(Mon.)		 Xilinx ISE WebPack
Ch08: Design Methodology and Tools (including CMOS Physical Design Styles),
Ch10: Datapath Subsystems (including Adders)
12/15~12/31 期末問卷調查		 8.8, and
10.1 ~ 10.2		 　
  • Deadline of Assignment #6
15 12/18
(Thu.)		 Tutorial #5
請到 1301A 上機使用 EDA 軟體
上課時間： 9:00am~10:00am		   Tutorial #5  
16 12/22
(Mon.)		 Ch11: Array Subsystems
12/15~12/31 期末問卷調查		 11.1 ~ 11.4 　 　
17 12/29
(Mon.)		 Ch11: Array Subsystems
12/15~12/31 期末問卷調查		 11.4 ~ 11.9 　 　
18 1/5
(Mon.)		 Ch09: Testing and Verification 9.1 ~ 9.7 　 　
19 1/12
(Mon.)		 期末考考試時間: 1月12日 (14:10 - 16:00) 請提早十分鐘到達考場
期末考考試地點: 1311 教室
注意(可以攜帶)：期末考可以攜帶教科書、其他書籍、講義、或紙張應考。
注意(不可攜帶)：考試時手機請關機，不得攜帶計算機、字典、電子字典、或其他電子產品應考。
 
(1/8~1/14 元智期末考週)		 　 　 　

 

last update: April 05, 2009