Instructor
Textbook
References
Grading Policy (subject to change)
Teaching Assistant
Classroom
Timetable (tentative and subject to change)
Week |
Date |
Topics |
Reading | Homework |
1 | 2/20 (Mon.) |
Semester started 開學 - 開始上課 |
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2/24 (Fri.) |
Syllabus HW-1 Descriptions Basic Unix/Linux Commands Introduction (incl. Cells/Blocks, Standard Cell Library) [Science-1983] Paper: (incl. Cell-Based Design Flow) VLSI_Ch13: Generalized Design Flow |
Ch01 ~ Ch02 |
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2 | 3/02 (Fri.) |
HW-1:
Description of the homework assignment VLSI_Ch01: nMOS, nMOS Layout, pMOS, pMOS Layout, CMOS Inverter and Its Layout, CMOS Logic Gates, Transistor-Level Schematic, Gate-Level Schematic, Standard Cell, Standard Cell Layouts, Standard Cell Library VLSI_Ch13: Generalized Design Flow [Science-1983] Paper: (incl. Cell-Based Design Flow, DRC, Placement, Routing) Unit-1: Introduction (pp. 1-23) (incl. Logic Synthesis, Physical Synthesis) |
Ch01 ~ Ch02 |
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3 | 3/09 (Fri.) |
Extra: Writing a Makefile Ch04: Fundamentals of Algorithms (incl. Mathematical Programming, LP, ILP, MILP, LP Relaxation, Branch-and-Bound, Cutting-Plane Algorithm, Convex Optimization Problem, Interior-Point Method) Ch12: Global and Detailed Routing (incl. General-Purpose Routing, Maze Routing, Lee's Algorithm, Line-Search Routing, A*-Search Routing, Global Routing Concepts) 黃信雄教授演講 (19:00~20:30) - Topic: "Wire Planning with Consideration of Electromigration and Interference Avoidance in Analog Circuits" |
4.5, 12.1 ~ 12.4 |
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4 | 3/16 (Fri.) |
HW-2: Description of the homework assignment Unit-1: Introduction (pp. 62-76) Ch12: Global and Detailed Routing (incl. Global Routing, Detailed Routing, Channel Routing) LAB: HW-3 (4:00pm ~ 6:30pm in 1301A, 19 students attended) |
12.4 ~ 12.5 |
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5 | 3/23 (Fri.) |
HW-2: Description of relevant information (incl. C++
Code, Data Structures, Algorithm, and STL) Ch12: Global and Detailed Routing (incl. Channel Routing) Ch11: Placement (incl. Introduction, Problem Formulations) LAB: HW-3 (4:00pm ~ 6:30pm in 1301A, 26 students attended) |
12.5, 11.1 ~ 11.2 |
|
6 | 3/30 (Fri.) |
Ch04:
Fundamentals of Algorithms (incl. Simulated
Annealing) Ch10: Floorplanning (incl. Floorplanning Basics, Problem Statement, Slicing and Non-slicing Floorplans, Normalized Polish Expression for Slicing Floorplans, SA-Based Floorplanning) Seminar: 陳彥光博士演講 (3:00pm~4:10pm) - Topic: "Energy-Efficient Memory Hierarchy for Multi-Core Architectures" |
4.4, 10.1 ~ 10.2 |
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7 | 4/06 (Fri.) |
Ch10: Floorplanning (incl.
Normalized Polish Expression for Slicing Floorplans, SA-Based
Floorplanning,
B*-Tree for Compacted Floorplans) |
10.1 ~ 10.2 |
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8 | 4/13 (Fri.) |
Ch10:
Floorplanning (incl. B*-Tree for Compacted Floorplans, Sequence
Pair for General Floorplans, Soft Modules) LAB: HW-3 (4:00pm ~ 7:00pm in 1301A) |
10.2, 10.4 |
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9 | 4/20 (Fri.) |
EDA Course-期中考 期中考考試時間: 4月20日 (13:10 - 15:00) 請提早十分鐘到達考場 期中考考試地點: 1401A or 1401B 教室 期中考考試範圍: Ch01, Ch02, Ch04, Ch10, Ch12, [Science-1983] Paper 注意:必須攜帶學生證應考,考試時手機請關機(手機開震動還是會有聲音),可以攜帶計算機、字典、電子字典、任何書籍、或紙張。 注意:完成考試的同學請盡速離開考場,並且勿在考場附近逗留、談話、或大聲喧嘩,影響他人考試者將扣平時分數。 (4/16~4/20 期中考週,本週停課) |
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10 | 4/27 (Fri.) |
Solving Midterm Exam Problems
(incl. B*-Tree, Normalized Polish Expression, Channel Routing,
A*-Search) Ch10: Floorplanning (incl. MILP Formulation Techniques, Floorplanning by Mathematical Programming) |
10.3 |
|
11 | 5/04 (Fri.) |
HW-4: Descriptions (Floorplanning via an MILP Solver) Ch10: Floorplanning (incl. Floorplanning by Mathematical Programming, Soft Modules) |
10.3 |
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12 | 5/11 (Fri.) |
Ch11: Placement (incl. Problem Formulations, Partitioning-Based Global Placement, The Fiduccia-Mattheyses Algorithm, Placement by Partitioning) | 11.1 ~ 11.3 | |
13 | 5/18 (Fri.) |
Ch03: Design for Testability (incl. Testability
Analysis, SCOAP Testability Analysis) |
3.1 ~ 3.2 |
|
14 | 5/25 (Fri.) |
HW-5: Descriptions
(Rectilinear Steiner Minimal Tree Construction) Ch03: Design for Testability (incl. SCOAP Testability Analysis, Probability-Based Testability Analysis) |
3.2 |
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15 | 6/01 (Fri.) |
Ch03: Design for Testability (incl. Scan Design, Muxed-D
Scan Design, Clocked Scan Design Logic BIST, Test Pattern Generation,
LFSR, Output Response Analysis) Seminar: "Trend, Green, Opportunity in EDA Semiconductor", by Willis Chang (張郁禮經理/博士), Cadence GM (7:00pm~8:30pm) |
3.3 ~ 3.4 |
|
16 | 6/08 (Fri.) |
(started at 2:10pm because of the CSE
graduation ceremony) HW-5: Descriptions and Minimum Spanning Trees Ch06: Logic Synthesis (incl. Introduction, Review of Truth Tables, Review of SOP and POS, On-set, Off-set, DC-set, cube, SOP Canonical Form, BDD) |
6.1 ~ 6.2 |
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17 | 6/15 (Fri.) |
HW-5: Descriptions and
Minimum Spanning Trees Ch06: Logic Synthesis (incl. Restriction, Positive and Negative Cofactors, Shannon Expansion, BDD, OBDD, ROBDD, The Algorithm for ROBDD Construction, Combinational Logic Minimization) |
6.2 ~ 6.3 |
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18 |
6/22 (Fri.) |
積體電路設計自動化導論 (EDA Course)- 期末考 考試時間: 6月22日 (13:10 - 15:00) 請提早十分鐘到達考場 考試地點: 1401A 或 1401B 教室 考試範圍: 教過的部份 (請見 http://www.itseng.org/YZU/CSE/Courses/2012/Spring/CS338A/) 注意:必須攜帶學生證應考,考試時手機請關機(手機開震動還是會有聲音),不得隨身攜帶電子產品(例如計算機、電子字典、手機)。可以攜帶書籍、講義、筆記、紙本的字典、或紙張。 注意:完成考試的同學請盡速離開考場,並且勿在考場附近逗留、談話、或大聲喧嘩,影響他人考試者將會被扣分數。 (6/18~6/22 期末考週,本週停課) |
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19 | 6/29 (Fri.) |
課程結束 |
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last update: June 15, 2012