CS338A - Introduction to IC Design Automation (EDA)

Spring 2012 (100-2 學期)
Department of Computer Science & Engineering
Yuan Ze University




Grading Policy  (subject to change)

Teaching Assistant


Timetable  (tentative and subject to change)




Reading Homework 
1 2/20
Semester started
開學 - 開始上課
HW-1 Descriptions
Basic Unix/Linux Commands
Introduction (incl. Cells/Blocks, Standard Cell Library)
[Science-1983] Paper: (incl. Cell-Based Design Flow)
VLSI_Ch13: Generalized Design Flow
Ch01 ~ Ch02
  • HW-1
2 3/02
HW-1: Description of the homework assignment
VLSI_Ch01: nMOS, nMOS Layout, pMOS, pMOS Layout, CMOS Inverter and Its Layout, CMOS Logic Gates, Transistor-Level Schematic, Gate-Level Schematic, Standard Cell, Standard Cell Layouts, Standard Cell Library
VLSI_Ch13: Generalized Design Flow
[Science-1983] Paper: (incl. Cell-Based Design Flow, DRC, Placement, Routing)
Unit-1: Introduction (pp. 1-23) (incl. Logic Synthesis, Physical Synthesis)
Ch01 ~ Ch02


3 3/09
Extra: Writing a Makefile
Ch04: Fundamentals of Algorithms (incl. Mathematical Programming, LP, ILP, MILP, LP Relaxation, Branch-and-Bound, Cutting-Plane Algorithm, Convex Optimization Problem, Interior-Point Method)
Ch12: Global and Detailed Routing (incl. General-Purpose Routing, Maze Routing, Lee's Algorithm, Line-Search Routing, A*-Search Routing, Global Routing Concepts)
黃信雄教授演講 (19:00~20:30) - Topic: "Wire Planning with Consideration of Electromigration and Interference Avoidance in Analog Circuits"
12.1 ~ 12.4
  • Deadline of HW-1 (3/9)
4 3/16
HW-2: Description of the homework assignment
Unit-1: Introduction (pp. 62-76)
Ch12: Global and Detailed Routing (incl. Global Routing, Detailed Routing, Channel Routing)
LAB: HW-3 (4:00pm ~ 6:30pm in 1301A, 19 students attended)
12.4 ~ 12.5
  • HW-2
  • HW-3
5 3/23
HW-2: Description of relevant information (incl. C++ Code, Data Structures, Algorithm, and STL)
Ch12: Global and Detailed Routing (incl. Channel Routing)
Ch11: Placement (incl. Introduction, Problem Formulations)
LAB: HW-3 (4:00pm ~ 6:30pm in 1301A, 26 students attended)
11.1 ~ 11.2
  • HW-3

6 3/30
Ch04: Fundamentals of Algorithms (incl. Simulated Annealing)
Ch10: Floorplanning (incl. Floorplanning Basics, Problem Statement, Slicing and Non-slicing Floorplans, Normalized Polish Expression for Slicing Floorplans, SA-Based Floorplanning)
陳彥光博士演講 (3:00pm~4:10pm) - Topic: "Energy-Efficient Memory Hierarchy for Multi-Core Architectures"
0.1 ~ 10.2
7 4/06
Ch10: Floorplanning (incl. Normalized Polish Expression for Slicing Floorplans, SA-Based Floorplanning, B*-Tree for Compacted Floorplans)
10.1 ~ 10.2
  • Deadline of HW-2 (4/09)
8 4/13
Ch10: Floorplanning (incl. B*-Tree for Compacted Floorplans, Sequence Pair for General Floorplans, Soft Modules)
LAB: HW-3 (4:00pm ~
7:00pm in 1301A)

10.2, 10.4
  • Deadline of HW-2 (4/09)
  • HW-3
9 4/20
EDA Course-期中考

: 4月20日 (13:10 - 15:00) 請提早十分鐘到達考場
期中考考試地點 1401A or 1401B 教室
Ch01, Ch02, Ch04, Ch10, Ch12, [Science-1983] Paper



10 4/27
Solving Midterm Exam Problems (incl. B*-Tree, Normalized Polish Expression, Channel Routing, A*-Search)
Ch10: Floorplanning (incl. MILP Formulation Techniques, Floorplanning by Mathematical Programming)


11 5/04
HW-4: Descriptions (Floorplanning via an MILP Solver)
Ch10: Floorplanning (incl. Floorplanning by Mathematical Programming, Soft Modules)
  • HW-4
12 5/11
Ch11: Placement (incl. Problem Formulations, Partitioning-Based Global Placement, The Fiduccia-Mattheyses Algorithm, Placement by Partitioning) 11.1 ~ 11.3  
13 5/18
Ch03: Design for Testability (incl. Testability Analysis, SCOAP Testability Analysis)
3.1 ~ 3.2
  • Deadline of HW-4 (May 20)
  • HW-5
14 5/25
HW-5: Descriptions (Rectilinear Steiner Minimal Tree Construction)
Ch03: Design for Testability (incl. SCOAP Testability Analysis, Probability-Based Testability Analysis)
  • Deadline of HW-4 (May 20)
15 6/01
Ch03: Design for Testability (incl. Scan Design, Muxed-D Scan Design, Clocked Scan Design Logic BIST, Test Pattern Generation, LFSR, Output Response Analysis)
Seminar: "Trend, Green, Opportunity in EDA Semiconductor", by Willis Chang (張郁禮經理/博士), Cadence GM (7:00pm~8:30pm)
3.3 ~ 3.4


16 6/08
(started at 2:10pm because of the CSE graduation ceremony)
HW-5: Descriptions and Minimum Spanning Trees
Ch06: Logic Synthesis (incl. Introduction, Review of Truth Tables, Review of SOP and POS, On-set, Off-set, DC-set, cube, SOP Canonical Form, BDD)
6.1 ~ 6.2
  • Deadline of HW-5 (June 10)

17 6/15
HW-5: Descriptions and Minimum Spanning Trees
Ch06: Logic Synthesis (incl. Restriction, Positive and Negative Cofactors, Shannon Expansion, BDD, OBDD, ROBDD, The Algorithm for ROBDD Construction, Combinational Logic Minimization)
6.2 ~ 6.3
  • Deadline of HW-5 (June 10)
18 6/22
積體電路設計自動化導論 (EDA Course)- 期末考

: 6月22日 (13:10 - 15:00) 請提早十分鐘到達考場
考試地點: 1401A 或 1401B 教室
考試範圍: 教過的部份 (請見 http://www.itseng.org/YZU/CSE/Courses/2012/Spring/CS338A/)



19 6/29
  • Deadline of HW-5 (June 29) [Extended!]


last update: June 15, 2012