Department of Computer Science & Engineering
Yuan Ze University
Instructor
Textbook
References
Grading Policy
Teaching Assistant
Venue
Timetable (subject to change)
Week |
Date (2009-2010) |
Topics |
Reading | Lab | Homework |
1 | 9/15 (Tue.) |
Ch01: Introduction, MOS Transistors, and CMOS Logic | 1.1 ~ 1.4 | ||
2 | 9/22 (Tue.) |
Ch01: CMOS Logic | 1.4 | Tutorial #1 | |
3 | 9/29 (Tue.) |
Ch01: CMOS Logic, CMOS Fabrication and Layout | 1.4 ~ 1.5 | ||
4 | 10/6 (Tue.) |
Ch01: CMOS Logic, CMOS Fabrication and Layout Ch03: CMOS Processing Technology |
1.5, and 3.1 ~ 3.2 |
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5 | 10/13 (Tue.) |
Ch01: CMOS Fabrication and Layout
(including Layout Design Rules, Stick Diagrams) |
1.5, and 3.3 |
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10/15 (Thu.) |
Tutorial #3 請到 1301A 上機學習使用 EDA 軟體 上課時間: 14:00~16:00 |
Tutorial #3 | |||
6 | 10/20 (Tue.) |
Ch02: MOS Transistor Theory | 2.1 ~ 2.3 | ||
7 | 10/27 (Tue.) |
Ch02: MOS Transistor
Theory Ch05: Circuit Simulation (HSPICE) |
2.4, and 5.1 ~ 5.2 |
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10/29 (Thu.) |
Tutorial #2 請到 1301A 上機學習使用 EDA 軟體 上課時間: 14:00~16:00 |
Tutorial #2 | |||
8 | 11/3 (Tue.) |
停課一次 (參加 NVIDIA GPU 研討暨用戶大會) |
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9 | 11/10 (Tue.) |
期中考(Midterm Exam) - VLSI Design 導論 期中考考試時間: 11月10日 (星期二) 14:10 - 17:00, 請提早十分鐘到達考場 期中考考試地點: 1401A 教室 注意: 必須攜帶學生證應考,考試時手機請關機,不得攜帶計算機、字典、電子字典、任何書籍或紙張。 注意: 完成考試的同學請盡速離開考場,並且勿在考場附近逗留或大聲喧嘩。影響他人考試者將扣期中考分數。 (期中考週:11月5日~11日) |
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10 | 11/17 (Tue.) |
檢討期中考考卷 Ch02: MOS Transistor Theory |
2.5 | ||
11/19 (Thu.) |
Tutorial #4 請到 1301A 上機學習使用 EDA 軟體 上課時間: 14:00~16:00 |
Tutorial #4 | |||
11 | 11/24 (Tue.) |
Ch02: MOS Transistor
Theory Ch05: Circuit Simulation (HSPICE) |
2.6 ~ 2.7, and 5.1 ~ 5.2 |
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12 | 12/1 (Tue.) |
Ch05: Circuit Simulation (HSPICE) | 5.2 | ||
13 | 12/8 (Tue.) |
Ch05: Circuit Simulation (HSPICE) Ch04: Delay Estimation |
5.2 ~ 5.3, and 4.1 ~ 4.2 |
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14 | 12/15 (Tue.) |
Ch04:
Logical Effort and Transistor Sizing LE: Chapter 1 of the Logical Effort book |
4.2 ~ 4.3 | ||
15 | 12/22 (Tue.) |
Ch04:
Logical Effort and Transistor Sizing LE: Chapter 1 of the Logical Effort book Ch04: Power Dissipation |
4.3 ~ 4.4 | ||
16 | 12/29 (Tue.) |
Ch04: Interconnect,
Wire Engineering Ch11: Array Subsystems (including SRAM) |
4.5, and 11.1 |
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17 | 1/5 (Tue.) |
Ch11: Array Subsystems
(including SRAM, DRAM, ROM, and Shift Registers) Ch06: Combinational Circuit Design (including nMOS inverter and Pseudo-nMOS inverter) |
11.1 ~ 11.5 |
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18 | 1/12 (Tue.) |
期末考(Final Exam) - VLSI Design 導論 期末考考試時間: 1月12日 (星期二) 14:10 - 17:00,請提早十分鐘到達考場 期末考考試地點: 1401A 教室 注意:必須攜帶學生證應考,考試時手機請關機(手機開震動還是會有聲音),不得攜帶計算機、字典、電子字典、任何書籍或紙張。 注意:完成考試的同學請盡速離開考場,並且勿在考場附近逗留或大聲喧嘩。影響他人考試者將扣平時成績。 (期末考週:1月7日~13日) |
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19 | 1/19 (Tue.) |
課程結束 |
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last update: January 27, 2010